This invention pertains to a semiconductor device with a so-called CMOS structure, where an n-channel insulating gate field-effect transistor (especially MOSFET) and a p-channel insulating gate field-effect transistor (especially MOSFET) are connected by common gate electrode wiring, and to a manufacturing method therefor.
FIG. 12 shows the partial schematic construction of a device with a conventional CMOS structure where an n-channel MOSFET and a p-channel MOSFET are connected by common gate electrode wiring.
As shown in FIG. 12(a), for example, p-type region 101a, as a structure called a well (or tank), and n-type region 101b are each provided on the principal face of p-type silicon semiconductor substrate 101. An element formation region is delineated for each region by field oxide film 102. Then in each element formation region, common gate electrode wiring 103 is provided with intervening gate oxide film 108. Then in the element formation region of p-type region 101a, a pair of n+ diffusion layers 104, that are implanted with ions of an n-type impurity at a relatively high concentration, is formed on both sides of gate electrode wiring 103. At the same time, a pair of p+ diffusion layers 105, that are implanted with ions of a p-type impurity at a relatively high concentration, is formed on both sides of gate electrode wiring 103 in the element formation region of n-type region 101b. These constitute an n-channel MOSFET and p-channel MOSFET source and drain, respectively.
When a structure such as this is manufactured, generally n+ diffusion layer 104 and p+ diffusion layer 105, that are separate element formation regions, are each covered by a resist (masked) and formed with ion implantation. But when n+ diffusion layer 104 is formed, in order to simplify and to make mask alignment easy, the photomask used when the well region discussed above was formed is used, n-type region 101b is covered by a resist and ion implantation performed, and when p+ diffusion layer 105 is formed, likewise p-type region 101a is covered by a resist and ion implantation is performed. In this case, during ion implantation, field oxide film 102 and the polycrystal (poly) silicon layer that constitutes gate electrode wiring 103 act as masks.
For example, as shown in FIG. 12(b) when ions of n-type impurity 106 are implanted in the element formation region of p-type region 101a, all of n-type region 101b is covered by photoresist 107 and ions are implanted in all of exposed p-type region 101a, forming n+ diffusion layer 104. On the other hand, when ions of a p-type impurity are implanted in the element formation region of n-type region 101b, conversely, all of p-type region 101a is covered by a photoresist and ions are implanted in all of exposed n-type region 101b, forming p+ diffusion layer 105.
Thus, n-type and p-type impurities are each implanted in the polysilicon layer that constitutes gate electrode wiring 103. Conventionally, as shown in FIG. 12(b) all of the polysilicon layer on p-type region 101a would become an n+ portion 103a, in which ions of an n-type impurity are implanted at a high concentration, and all of the polysilicon layer on n-type region 101b would become a p+ portion 103b, in which ions of a p-type impurity are implanted at a high concentration.
For the gate electrode wiring discussed above, polycide wiring where the upper part of the polysilicon layer is silicided is normally used.
On the other hand, particularly in the case of titanium silicide, there has been the problem that, in order for the siliciding reaction to proceed and give lower resistance, crystal structure phase transition is necessary. But, for example, when the wire width is made smaller in order to make the gate narrower, it becomes hard to cause this phase transition, and the siliciding reaction stops, leaving relatively high resistance.
This dependence of titanium silicide on wire width also affects impurities in the polysilicon layer. It is especially noticeable in the case of n-type impurities, such as arsenic (As) and phosphorus (P). For example, if wire width is reduced to less than 0.5 xcexcm, the rate of formation of low-resistance titanium silicide becomes poor. On the other hand, in the case of p-type impurities, such as boron (B), such a large effect does not occur and it is possible to form wires as thin as 0.3 xcexcm, for example.
In addition, even with polysilicon layers doped with n-type impurity, there have been problems in that those on field oxide films have a poorer rate of low-resistance titanium silicide formation than those formed on element formation regions, and their formation states vary.
Due to these facts, with the partial schematic construction of a device with a conventional CMOS structure as shown in FIG. 12, if, for example, the width of gate electrode wiring 103 is made narrower in order to make gate width narrower, there has been the problem that the rate at which a titanium silicide layer, in particular, is formed in this gate electrode wiring 103 would be poor. For CMOS semiconductor devices currently manufactured, since there are regions into which n+ ions are implanted on field oxide films, this has been a hindrance to making smaller elements, along with the drop in the siliciding reaction that accompanies the making of electrode wiring thinner, such as discussed above. Regions doped with n-type impurity, for example, such as of a DRAM formed in a p-type silicon well, become appreciably larger than regions doped with p-type impurity. Thus, using a manufacturing method such as discussed above, the area in which ions of an n-type impurity are implanted in a polysilicon layer, that is the electrode wiring, becomes larger, the conductor wiring region where the rate of formation of low-resistance titanium silicide is poor increases, and this would be one obstacle to making smaller elements.
So the objective of this invention is to provide a semiconductor device with a structure that is comparatively beneficial for forming a silicide layer, such as titanium silicide, in the common gate electrode wiring of CMOS structures, and to provide a manufacturing method therefor.
With the semiconductor device of this invention that is to solve the problems discussed above, being a semiconductor device where an n-channel insulating gate field-effect transistor and a p-channel insulating gate field-effect transistor are connected by common gate electrode wiring on the principal face of a semiconductor substrate, in the polycrystal silicon layer that constitutes said gate electrode wiring, n-type impurity is introduced into the element region of said n-channel insulating gate field-effect transistor and p-type impurity is introduced into the element region of said p-channel insulating gate field-effect transistor.
In addition, the semiconductor device manufacturing method of this invention has a process wherein a field region is formed on the principal face of a semiconductor substrate that has a first region of a first conductive type and a second region of a second conductive type and a first element region is delineated for said first region and a second element formation region is delineated for said second region, a process wherein, after gate insulating films are formed for said semiconductor substrate surface in said first and second element formation regions, a polycrystal silicon layer is formed into a gate electrode wiring pattern that extends through said first and second element formation regions on these gate insulating films and on said field region, a process wherein, after a mask is formed to cover said first element formation region, a first impurity of a first conductive type is introduced into said polycrystal silicon layer on said second element formation region and on said field region and into said semiconductor substrate surface region on both sides of said polycrystal silicon layer in said second element formation region, and a process wherein, after a mask is formed to cover said second element formation region and said field region, a second impurity of a second conductive type is introduced into said polycrystal silicon layer on said first element formation region and into said semiconductor substrate surface region on both sides of said polycrystal silicon layer in said first element formation region.